Manager, ASIC Sustaining engineer, Silicon Operations

Leo is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity.

Export Control Requirement

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

The Silicon Operations team is seeking a Manager,ASIC Sustaining Engineer who has the responsibility for Yield improvement to meet or beat target and Root Cause Analysis for Yield excursions across Wafer, Assembly and Test.

Use statistical tools and data analysis to identify yield limiters and trends in electrical test and in-line inspection data.

Conduct failure analysis (FA) on defective wafers and devices to identify the source of, or prevent, yield excursions.

Design and execute experiments (DOE) to optimize manufacturing processes and reduce particle contamination.

Partner with process, equipment, and design engineers to implement solutions to improve, maintain, or troubleshoot production lines.

Install, qualify, and maintain in-line defect inspection and review equipment.

Create and maintain specifications, process documentation, and best-known methods

Key job responsibilities

Lead team to identify root cause for chip performance / yield / quality issues.

Analyze CP test bin / data log to identify failure mode.

Electrical failure analysis and physical failure analysis to locate suspect process stage

Work with appropriate supplier to define corrective actions / solutions.

Trace action implementation to verify effectiveness.

Product early-stage design support to help product tape-out smoothly and Si success

• Design rule review & assessment for robust product design
• Layout review or DFM to enlarge manufacturing window
• Yield window characterization and device sweet spot identification for the best yield / performance process condition.