AIML enhanced Design/Verification Methodology Engineer

Join HPE as an AIML enhanced Design/Verification Methodology Engineer. In this high-impact role, you will develop and execute comprehensive verification strategies for complex digital designs using AIML methodologies. You will architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure, and collaborate closely with design and system engineering teams. This position offers a hybrid work model, competitive benefits, and opportunities for personal and professional development.

• Develop and execute comprehensive verification strategies for complex digital designs using AIML enhanced methodologies.
• Architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure.
• Use both “classical” and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI based infrastructures.
• Proven ability to develop and drive verification plans to closure
• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent)
• Strong proficiency in SystemVerilog for verification (classes, constraints, functional coverage, assertions/SVA)
• Experience verifying high-speed serial interfaces or protocol-level IP blocks
• Master's or Ph.D. in Electrical Engineering or Computer Science
• 1 - 5 years of hands-on Design/Verification experience in an ASIC or SoC environment
• Knowledge of scripting languages (Python, Perl, TCL) for automation of verification workflows and regression infrastructure
• Academic or professional class projects or coursework in networking, communication protocols (e.g., Ethernet, PCIe, USB, AMBA/AXI, SPI, I2C, UART), or related areas
• Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce)
• Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints)
• Effective communication and collaboration skills in cross-functional team settings
• Deep familiarity with AIML concepts and workflows — including awareness of agentic workflows, APIs, model selection, etc
• Familiarity with formal verification tools and techniques (e.g., JasperGold, VC Formal)
• Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
• Contributions to verification methodology development or published work in the field
• Experience with power-aware verification (UPF/CPF) or mixed-signal verification