Hardware Engineer (FPGA)

Join our team as an FPGA Design Engineer, where you will be responsible for bridging the gap between RTL and physical silicon. You will bring our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development. Your role will encompass the entire FPGA lifecycle, including hardware platform selection, complex RTL implementation, lab debugging, and software development. You will work closely with our silicon, EDA, and research teams, and your expertise will be crucial in driving our innovative projects forward.

• As an FPGA Design Engineer, you will be responsible for the following key missions:
• 1. Owning the bridge between RTL and physical silicon, bringing physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development.
• 2. Leading the selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development, and adapting and implementing complex ASIC RTL onto FPGA targets.

1. Building FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments, and developing the software layer around the hardware.

• Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog)
• Strong Python for automation, test, and build tooling
• Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces
• Strong board-level bring-up and lab debugging skills on real hardware
• Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics
• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment
• CI/CD for hardware (GitLab CI, Docker-based build and test)
• SERDES tuning and signal integrity fundamentals
• Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute
• Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines
• Verification frameworks like Cocotb, UVM, or OSVVM