Design Verification Engineer

Join Normal as a Design Verification Engineer, where you will verify our innovative physics-inspired ASICs and set the quality standards for our AI models. You will own the design verification process, review AI-generated verification collateral, and support customer deployments. This role requires proven expertise in end-to-end design verification, advanced proficiency in SystemVerilog and EDA verification tools, and excellent communication skills.

• Assurer la vérification de la conception des ASICs inspirés par la physique de l'entreprise, en supervisant les environnements de test, les assertions et la couverture fonctionnelle.
• Collaborer avec les équipes de ML et de produit pour examiner les documents de vérification générés par l'IA et façonner la stratégie produit.
• Définir des rubriques, sélectionner des exemples d'or et collaborer avec l'équipe de données pour garantir que nos modèles apprennent à partir d'artefacts de vérification.
• Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
• Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
• Willingness to occasionally support customer-facing deployment work, including some travel
• Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session
• 5+ years of experience in digital verification at a major semiconductor or EDA tool company
• Hands-on use of LLMs or agentic tools in verification workflows
• Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
• Exposure to analog, mixed-signal, or unconventional compute verification