Hardware Engineer (RTL)

Join Normal as an RTL Design Engineer, where you will design and verify the digital logic at the core of our thermodynamic hardware. This role involves writing synthesizable SystemVerilog, authoring verification environments, collaborating with architecture and physical design, and participating in design reviews. You will have the opportunity to shape architecture and work closely with first-principles decisions.

• Design and verify digital logic for thermodynamic hardware, including writing synthesizable SystemVerilog and authoring verification environments.
• Collaborate with architecture and physical design teams to ensure functionality and physical realizability of designs, and participate in design reviews.
• Support tapeout preparation, integration, and post-silicon bring-up, and contribute to architecture decisions beyond implementation.
• The strongest candidates have taped out silicon, written both RTL and testbenches, and are comfortable working in an environment where the specification is still being developed in parallel
• This is a role for an engineer who does not draw a hard line between design and verification
• At least one tapeout in your background, from any node and any company size
• Comfort operating across both design and verification without treating them as separate disciplines
• Strong debugging instincts across simulation, waveforms, and formal counterexamples
• Industry experience in ASIC or SoC design
• Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
• Ability to work directly with architects and physical designers without needing a large intermediary layer
• Experience authoring verification environments in UVM, cocotb, formal, or equivalent, not just running existing testbenches
• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
• Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
• Experience at an AI chip company where design and verification were tightly coupled
• Familiarity with RISC-V or other open ISAs
• Experience with AI-assisted RTL or EDA tooling in your design workflow
• Exposure to physical design constraints, floorplanning, or timing-driven RTL development