Staff Engineer (RTL Implementation)

Join our CPU design team as a Staff Engineer (RTL Implementation). You will work on a CPU based on RISC-V ISA, collaborating with various teams to deliver a functional, timing, and power-converged design. Your responsibilities will include synthesis and initial place and route for new and legacy designs, optimizing core configurations for best PPA, and enhancing the physical design environment. This role offers end-to-end exposure to CPU design and hands-on experience optimizing CPU designs. Candidates with various experience levels are welcome to apply.

• Collaborate with core micro-architects to refine CPU core configurations and optimize power, performance, and area (PPA).
• Perform synthesis and initial place and route for new and legacy designs, and drive physical design experiments.
• Enhance physical design environment, tools, and methodologies to improve development efficiency.
• We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
• Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis
• Skilled in synthesis, place and route tools including flows and physical design methodology
• Background in CPU micro-architecture
• Experienced in high-performance physical design