Senior Staff Design Verification Engineer

Join our innovative company as a Senior Staff Design Verification Engineer. You will have the opportunity to work on a groundbreaking architecture in the field of in-memory computing. We are committed to building a culture of transparency, inclusiveness, and intellectual honesty, while ensuring that our team members are always learning and having fun. As a member of our team, you will receive equity, health care, flexible time-off, paid paternity leave, a 401k retirement plan, and the option for remote or hybrid work.

• Conception et mise en œuvre de l'environnement de vérification des SoC, y compris la création de tests et la mise en œuvre de la vérification.
• Collaboration avec les équipes d'architecture et de conception pour s'assurer que les spécifications sont respectées et que les exigences de vérification sont satisfaites.
• Direction et mentorat d'une équipe d'ingénieurs en vérification, en fournissant des conseils techniques et en favorisant le développement professionnel.
• BS in Electrical Engineering, Computer Science or related field with 12 + years of Industry experience or MS Electrical Engineering, Computer Science or related field preferred with 7 + years industry experience
• Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology
• Passionate about AI and thriving in a fast-paced and dynamic startup culture
• Experience in SoC verification cycle from architecture to tape out to bring up
• Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM)
• Good problem-solving skills, and the passion to take on challenges (particularly in AI domain)
• Good knowledge of verification methodologies such as UVM/OVM etc
• Hands on ASIC-SoC Design verification tests and debug experience
• Experience with C/C++, SystemC (a big plus!)
• Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts