Senior Staff PCB Layout Design Engineer

Join d-Matrix as a Senior Staff PCB Layout Design Engineer, where you will lead the layout of high-complexity, high-layer-count PCBAs and drive the automation, tooling, and constraint management processes for hardware development. You will work on ultra-high-speed interfaces, power delivery optimization, and act as the primary interface with PCB fabricators and CMs. This is a senior leadership role that offers equity, health care, flexible time-off, and a remote/hybrid working model.

• Lead the layout of high-complexity, high-layer-count PCBAs, ensuring signal integrity and power delivery.
• Drive the automation, tooling, and rigorous constraint management processes that allow for scalable hardware development.
• Act as the primary interface with PCB fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production.
• Education: BS in Electrical/Electronic Engineering or equivalent practical experience
• Mastery of Constraints: Expert-level proficiency in Cadence Allegro Constraint Manager, including the setup of complex T-junctions, differential pair phase-tuning, and Z-axis delay matching
• Experience: 12+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
• Automation Skills: Proven ability to write and deploy SKILL scripts or utilize Allegro’s API to automate design audits and layout routines
• Technical Depth: * Deep understanding of high-speed routing (back-drilling, via-in-pad, and skip-vias)
• Familiarity with PLM/PDM integration for managing layout releases and ECO (Engineering Change Order) workflows
• Experience establishing a Library Management System and standardized footprint/padstack creation processes
• Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs
• Proven track record of successfully routing 112G SerDes and complex DDR5/HBM interfaces
• Experience with HDI (High-Density Interconnect) and ELIC (Every Layer Interconnect)