FPGA Prototyping Engineer

Join Specs Inc., a leading augmented reality company, as an FPGA Prototyping Engineer. In this role, you will port complex SoC RTL onto FPGA, HAPS, and ZeBu platforms, enable boot and software validation flows, and collaborate across various teams. You will also develop and integrate low-level embedded software, debug hardware/software issues, and participate in designing and maintaining SoC validation tests. This position offers a comprehensive benefits package, including generous time off, medical coverage, and a 401(k) plan.

• Port complex SoC RTL onto FPGA, HAPS, and ZeBu platforms, enabling boot and software validation flows.
• Build and maintain pre-silicon platforms that enable early firmware software development, bootloader/FSBL bring-up, and validation of key interfaces.
• Debug complex hardware/software bring-up issues across HAPS, ZeBu, and FPGA targets, including memory-model integration, reset and clock sequencing.
• Experience with Static timing analysis for XILINX/Intel FPGA platforms
• Familiarity with ARM Cortex-M/R/A architectures, SoC peripherals, and system interfaces such as LPDDR/DFI, eMMC, PCIe, JTAG/SWD, UART, SPI, I2C/I3C, GPIO, and QSPI Flash
• Strong understanding of SoC RTL integration and the tradeoffs required to map large designs onto prototyping and emulation platforms
• Ability to work from RTL, hardware schematics, datasheets, and timing reports, and to communicate platform limitations and integration constraints clearly across hardware and software teams
• Experience debugging clocks, resets, timing issues, waveforms, platform bring-up problems, and embedded software crashes or asserts across multiple pre-silicon targets
• Proficiency in embedded C/C++ and ability to read, write, and debug low-level firmware for boot, diagnostics, drivers, and hardware validation
• Hands-on experience with FPGA prototyping and hardware emulation platforms such as HAPS, ZeBu, or similar Cadence/Siemens/Synopsys environments
• Experience with bare-metal development and boot flows, including boot ROM/FSBL, startup code, linker scripts, memory maps, MMU/MPU/cache configuration, and board support packages
• Familiarity with debugging tools such as JTAG/SWD, GDB, trace, logic analyzers, waveform viewers, embedded logging, and diagnostic frameworks
• Strong problem-solving, communication, teamwork, and prioritization skills in a fast-paced cross-functional environment
• Experience with RTOS concepts and development, including task/thread scheduling, interrupts, synchronization, timers, memory management, device-driver integration, and real-time constraints
• Demonstrated experience in C/C++ programming for embedded, bare-metal, or RTOS-based systems
• Experience with RTL integration, FPGA prototyping, hardware emulation, or pre-silicon validation
• Experience running embedded software, diagnostics, or RTOS-based applications on FPGA or emulator platforms
• Experience with Synopsys ZeBu and Synopsys HAPS platforms; experience with other Cadence, Siemens, or Synopsys emulation/prototyping environments is a plus
• 5+ years of experience in SoC prototyping, FPGA/emulation bring-up, embedded software, firmware, or pre-silicon validation
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Experience bringing up complex SoC or subsystem designs on non-silicon targets and debugging boot, firmware, RTOS, and hardware/software interface issues using waveforms, JTAG/SWD, logs, and trace
• Experience with RTOS platforms such as FreeRTOS, Zephyr, ThreadX, QNX, or similar, including BSP/device-driver integration and real-time profiling
• Experience with ARM Cortex-M/R/A architectures, bootloader/FSBL development, memory subsystems such as LPDDR/DFI, and storage or high-speed interfaces such as eMMC and PCIe
• Experience building or maintaining CI/CD pipelines for hardware prototyping and embedded software flows, such as GitLab or TeamCity
• Experience working closely with system software teams on early boot, FSBL, driver, RTOS, and validation enablement