DFT Intern (12 Week Internship)

Join Etched as a DFT Intern for a 12-week paid internship. You will help review and refine DFT flow automation, work across frontend and backend design teams, and contribute to DFT verification. This internship offers a competitive salary, equity, unlimited PTO, life insurance, and full medical, dental, and vision coverage.

• Assister à la révision et à l'amélioration de l'automatisation du flux DFT pour soutenir la régression au niveau des puces.
• Collaborer avec les équipes de conception frontend et backend, contribuer à la vérification DFT et développer des flux pour divers modèles de défaut ATPG.
• Participer à la recherche et au développement en contribuant aux efforts techniques de l'entreprise.
• You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment
• Exposure to ASIC or SoC design concepts
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence
• Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
• Familiarity with digital logic design fundamentals
• Familiarity with a hardware description language (Verilog or SystemVerilog)
• Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field
• Familiarity with scripting in Python, Tcl, or another language
• We encourage you to apply even if you do not believe you meet every single qualification
• Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
• Experience with Tessent or similar DFT tooling
• Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
• Familiarity with clocking and reset schemes
• Exposure to DFT flow automation or regression infrastructure