Design Verification Engineer

# Design Verification Engineer
> Weekday AI · Bengaluru, India · Full-time · Posted 2026-07-15
**Workplace:** on_site
**Department:** Weekday's Client via platform
## Description
**This role is for one of the Weekday's clients**
Min Experience: 4+ years

Location: Bengaluru

JobType: full-time
## Requirements
Exp: 4+ years hands-on experience in ASIC/SoC Front-End Verification.
Skills: Hands on expertise of System Verilog (SV) and UVM.
Protocols: Strong working knowledge of AMBA CHI / AXI protocols and cache coherency concepts.
Interface Domain: Proven experience in verifying high-speed memory interfaces (LPDDR5) or peripheral protocols (PCIe/UCS).
Domain : Proven track record of verifying complex SoCs and GPU sub-systems (specifically experience interfacing with or verifying NVIDIA GPU architectures is highly preferred).
Skills : Expertise in SystemVerilog (SV) and UVM architecture, including building testbenches from scratch.
Protocols & IPs : Deep understanding of high-speed interconnects, memory controllers (e.g., DDR, HBM), and standard bus protocols (e.g., AXI, ACE, CHI ).
Coverage & Sign-off : Expert-level knowledge in defining functional coverage metrics, writing assertions, and debugging code coverage gaps.
Tools : Synopsys VCS, Cadence Xcelium, or Siemens Questa and debuggers like Verdi.
### Must-have skills

System Verilog, UVM

### Good-to-have skills

GPU Verification, RISC-V, PCIe

## Apply
[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/28C3B1FEF7/apply)
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