SOC集成工程师

Responsibilities: 1. Responsible for Front-End chip integration and implementation, including design, implementation and execution of the FE flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design; 2. Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology. Qualifications: 1. Familiar with Verilog RTL design and has experience of large digital ASIC project; 2. Familiar with Front-End flows (Synthesis/Timing/LEC/CDC/DFP/ECO etc.) and EDA tools (DesignCompiler/Genus,PrimeTime, Formality/Conformal, Spyglass/0in, VCLP, ICC2/FC/Innovus etc.); 3. Familiar with unix/linux and scripts (tcl, perl or python etc.); 4. Experience in Back-End flow is a plus; 5. Experience in high-performance computing design/interfacing IP is a plus; 6. Fluent English on talking, presentation and writing documents; 7. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager; 8. Master with at least 3 years or Bachelor with at least 5 years working experience in ASIC area.