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Technical Lead, Power Analysis and Optimization

careers.cisco.com · San Jose, California, United States of America

External listingFull-time2 months ago

About The Role

Join us as an ASIC Design Technical Leader and drive the development of next-generation silicon architectures for web-scale and service provider networks. Collaborate with top-tier engineers, leverage your expertise in SDC, timing constraints, and ASIC design, and shape the future of innovative networking chip technology.

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